1. Field of the Invention
The present invention is related to supporting input/output (I/O) slots in computer systems, and, in particular, supporting multiple I/O peripheral component interconnect (PCI) slots without adding latencies while providing for new and existing I/O requirements.
2. Description of the Related Art
PCI is described in the PCI Local Bus Specification, Revision 2.2 (hereinafter the General PCI Specification) available from the PCI Special Interest Group. The PCI bus has sufficient data bandwidth for high performance peripherals, such as a video controller, high speed network interface card(s), hard disk controller(s), SCSI adapter, wide area network digital router, and the like. The PCI bus can operate at 33 MHz or 66 MHz. A PCI bus operating at 33 MHz may have a plurality of card connectors (or slots) attached thereto. But, as sophisticated graphics and increased network data transfer requirements place upward pressure on the PCI buses for faster data transfers between the computer system main memory, host processor(s), peripherals, and data from other computers on the network, 66 MHz operation is preferred, and in some cases mandatory. When the PCI bus runs at 66 MHz, however, the number of card connectors is limited to two because of the timing constraints of the digital control signals. Therefore, a plurality of PCI-to-PCI bus bridges is required to provide enough PCI device card connectors for a typical computer system, such as a network server or graphics workstation. These PCI-to-PCI bus bridges create new PCI bus numbers and introduce increasingly complex data protocol and handshake requirements, multiple delayed transactions, additional bus latency, and potential deadlock cycles.
PCI-X (extended PCI) is described in the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0 (hereinafter the PCI-X Specification), also available from the PCI Special Interest Group. Similar to the 66 MHz PCI bus, the PCI-X bus is designed to provide connectivity to even higher bandwidth devices, such as three-dimensional (3D) graphics and gigabit I/O devices. Both the 66 MHz PCI and the PCI-X buses are considered as compatible supersets of the standard PCI bus with minimal differences. To identify 66 MHz PCI or PCI-X devices, one static signal is added by defining an existing ground pin, and one bit is added to the Configuration Status register. Bus drivers are basically the same as for 33 MHz operation, but require faster timing parameters and redefined measurement conditions. As a result, the limited number of connectors (e.g., 1 or 2) mentioned above is recommended.
PCI-X buses include their own logic circuits and signal protocols. According to the PCI-X Specification, all signals are sampled on the rising edge of the PCI bus clock and only the PCI-X version of these signals is used inside PCI-X devices. In the current General PCI Specification, there are many instances in which the state of an input signal setting up to a particular clock edge affects the state of an output signal after that same clock edge. This type of I/O signal behavior is not possible in a PCI-X interface. Thus, PCI-X introduces the concept of a clock-pair boundary, which replaces some single-clock-edges where control signals change. Timing on the PCI-X bus is not as critical as for the aforementioned 66 MHz PCI in the General PCI Specification, even when the PCI-X bus runs faster than 133 MHz. The PCI-X Specification allows PCI bus operation with more than two PCI device cards.
In server environments, Microsoft Corporation has been championing so-called dynamic hardware partitioning (DHP) as the next generation system architecture. DHP enables multiple operating system instances in one server. One issue is to determine how to support multiple I/O (PCI) connectors without adding additional latencies and cost while still satisfying the existing and new I/O requirements. Currently, there are no PCI bridges that support DHP.